Analog-to-digital converters (ADCs) are useful components in any circuit or system that interfaces analog and digital circuitry and signals. One application in which analog-to-digital converters are particularly useful includes imaging devices such as CMOS and CCD imagers. Imagers typically convert light photons into analog image signals. These analog image signals are converted to digital signals, by an analog-to-digital converter, and then processed by an image processor or other processing circuitry.
There is a desire to increase the speed of the analog-to-digital conversion process in many applications such as e.g., imagers. As such, many applications use pipelined analog-to-digital converters, which typically operate faster than non-pipelined analog-to-digital converters. FIG. 1 is an illustration of a conventional N-bit pipelined analog-to-digital converter 10. The pipelined analog-to-digital converter 10 consists of multiple low resolution (e.g., 1.5 bits) stages 121, 122, . . . , 12n, . . . 12N-1, each of which comprises an arithmetic unit 20 and a two-level decision circuit 40. The pipelined analog-to-digital converter 10 further includes digital correction logic 14 for outputting an N-bit digital code representing an input analog signal.
FIG. 1 illustrates the components of the nth stage 12n in more detail. It should be appreciated that the other stages 121, 122, . . . , 12N-1 contain the same circuitry as the nth stage 12n. The arithmetic unit 20 comprises a switching block 22, four additional switches 24, 26, 28, 30, a sampling capacitor Cs, a feedback capacitor Cf, and an operational amplifier 32. The decision circuit 40 includes two comparators 42, 44 and an encoder 46.
In operation, the arithmetic unit 20 in the first stage 121 merely operates as a sample and hold circuit. In the other stages 122, . . . , 12n, . . . 12N-1, the arithmetic unit 20 multiplies the incoming analog signal portion VRES(n-1), often referred to as a “residue,” by a factor of two and subtracts from this product one of three voltages +VR, 0, −VR, based on the closed switch in the switching block 22. The switches of block 22 are opened/closed based on the decision bits Dn-1 from a prior stage (e.g., stage 12n-1). The new residue is fed into the decision circuit 40, where it is compared with two different reference voltages ¼VR, −¼VR. The encoder generates and outputs decision bits Dn for the stage 12n. The decision bits for each of the stages 121, 122, . . . , 12n, . . . 12N-1 are processed by the digital correction logic 14, which removes any redundancy and outputs the N-bit digital output code.
As can be seen in FIG. 1, the conventional pipelined analog-to-digital converter 10 requires one operational amplifier 32 for each stage 121, 122, . . . , 12n, . . . 12N-1 in the pipeline. The majority of the power of the pipelined analog-to-digital converter 10 is consumed by operational amplifiers 32. Therefore, minimizing the power consumption of the operational amplifiers 32 is key to the design of low power pipelined analog-to-digital converters 10.
FIG. 2 illustrates the timing diagram for two stages STAGE 1, STAGE 2 of the FIG. 1 pipelined analog-to-digital converter 10. Non-overlapping clock signals PHI1, PHI2 are used to control the switching circuitry contained within each stage STAGE 1, STAGE 2 to configure how the sampling and feedback capacitors Cs, Cf and the operational amplifier 32 are connected.
FIG. 3 illustrates the operational amplifier configuration of the two stages STAGE 1, STAGE 2 when the second clock signal PHI2 is asserted (i.e., has a high level). As can be seen in FIGS. 2 and 3, the first stage STAGE 1 undergoes a sampling operation while the second stage STAGE 2 undergoes an amplifying operation. That is, the first stage's arithmetic unit 201 is configured such the analog input voltage Vin is sampled in the sampling capacitor Cs. The second stage's arithmetic unit 202 is configured in a manner such that the operational amplifier 32 amplifies the signal stored in the sampling capacitor Cs and outputs the amplified signal as Vout.
FIG. 4 illustrates the operational amplifier configuration of the two stages STAGE 1, STAGE 2 when the first clock signal PHI1 is asserted (i.e., has a high level). As can be seen in FIGS. 2 and 4, the first stage STAGE 1 undergoes the amplifying operation while the second stage STAGE 2 undergoes the sampling operation. That is, the first stage's arithmetic unit 201 is configured such the signal stored in the sampling capacitor Cs is amplified by the operational amplifier 32. The second stage's arithmetic unit 202 is configured to sample the output from the first stage STAGE 1 and store it in the stage 2 STAGE 2 sampling capacitor Cs.
It can be seen from FIGS. 3 and 4 that during the sampling operations, the operational amplifiers 32 performs no useful function; they just consume power. This occurs because the operational amplifiers 32 are placed into an open-loop configuration with their inputs and outputs connected to known voltage levels. To avoid wasting power during every sampling operation, some analog-to-digital converters share one operational amplifier 32 between two adjacent stages STAGE 1, STAGE 2 as us shown in FIGS. 5 and 6.
FIGS. 5 and 6 illustrate a circuit 120 of a pipelined analog-to-digital converter in which arithmetic units 201, 202 of two pipeline stages STAGE 1, STAGE 2 share one operational amplifier 32. The amplifier 32 can be shared because the circuit 120 contains six switches S1, S2, S3, S4, S5, S6 that are controlled to connect the sampling and feedback capacitors Cs, Cf to the operational amplifier 32 inputs and outputs differently depending on the operation being performed.
FIG. 5 illustrates the circuit 120 when the second clock signal PHI2 of FIG. 2 is asserted. While the second clock signal PHI2 is asserted, switch S1 is closed to connect the analog input voltage Vin to the stage 1 arithmetic unit 201 sampling capacitor Cs. Switches S5 and S6 are closed in the second stage's arithmetic unit 202 such that the operational amplifier 32 amplifies, and outputs as Vout, a signal stored in the stage 2 arithmetic unit 202 sampling capacitor Cs. The other switches S2, S3 and S4 are left open. Thus, as can be seen in FIGS. 2 and 5, the first stage STAGE 1 undergoes a sampling operation while the second stage STAGE 2 undergoes an amplifying operation, but only one operational amplifier 32 is connected and used.
FIG. 6 illustrates the circuit 120 when the first clock signal PHI1 of FIG. 2 is asserted. While the first clock signal PHI1 is asserted, switches S1, S5 and S6 are open, and switches S2, S3 and S4 are closed. As such, the first stage's arithmetic unit 201 is configured such that a signal stored in the first stage arithmetic unit 201 sampling capacitor Cs is amplified by the operational amplifier 32 and output as Vout. The second stage's arithmetic unit 202 is configured to sample and store an analog input Vin in the stage 2 STAGE 2 sampling capacitor Cs. As can be seen in FIGS. 2 and 6, the first stage STAGE 1 undergoes the amplifying operation while the second stage STAGE 2 undergoes the sampling operation. Again, only one operational amplifier 32 is connected and used during these operations.
By sharing an operational amplifier 32 between adjacent two stages STAGE 1, STAGE 2, the power consumption of the pipelined analog-to-digital converter 10 (FIG. 1) can be reduced by half. However due to the finite DC gain Ao and input parasitic capacitance Cp of the operational amplifier 32 (FIG. 7b), the previous output Vo(k−1) adversely effects the present output Vo(k), which is known in the art as the “memory effect.” The memory effect can cause a non-linearity in the operational amplifier 32 and thus, analog-to-digital converter output.
Briefly, the memory effect can be described using the following equations in reference to FIG. 7a. Ideally, during sampling, charge should be represented as Q=(Cf+Cs)×Vin. From charge conversion, at the amplifying phase, Q=Cf×(Vo−Vx)−Cp×Vx−Cs×Vx=(Cf+Cs)×Vin, where Vx is the input node voltage of the operational amplifier 32. Because the amplifier has a finite gain Ao, Vo=−Ao×Vx−>Vx=−Vo/Ao. This means that Cf×(Vo+Vo/Ao)+Cp×Vo/Ao+Cs×Vo/Ao=(Cf+Cs)×Vin. Therefore, Vo=Vin×(Cf+Cs)/(Cf+(Cf+Cs+Cp)/Ao), which equals Vin×Gc.
In reality, however, there is charge associated with parasitic capacitance Cp (due to the memory effect). As such, at the sampling stage, as shown in FIG. 7b, Q=(Cf+Cs)×Vin(k)−Cp×Vin_err(k), where Vin_err(k) is the memory error associated with the parasitic capacitance Cp. Using just the error term, from charge conversion, Vo(k)=−Vin_err(k)×Cp/(Cf+(Cf+Cs+Cp)/Ao)˜=−Vin_err(k)×Cp/Cf, if Ao is large enough. For the first and second terms Vo(k)=Vin(k)×Gc−Vin_err(k)×Cp/(Cf+(Cf+Cs+Cp)/Ao). Since Vin_err(k) comes from the previous output, Vin_err(k)=−Vo(k−1)/Ao=−Gc×Vin(k−1)/Ao. Accordingly, Vo(k)=Vin(k)×Gc+Vin(k−1)×Gc/Ao×Cp/(Cf+(Cf+Cs+Cp)/Ao)=Vin(k)×Gc+Vin(k−1)×Gc×e, where e=1/Ao×Cp/(Cf+(Cf+Cs+Cp)/Ao)˜1/Ao×Cp/Cf. It should be noted that the second order error are neglected in the above calculations.
In addition, charge injection and kickback noise from the circuitry add to the memory effect error described above. Reducing the memory effect is a key element in designing a pipelined analog-to-digital converter that shares operational amplifiers between two pipeline stages. Accordingly, there is a need and desire for a pipelined analog-to-digital converter that shares an operational amplifier between two pipeline stages, yet does not suffer from the memory effect and the problems associated with the memory effect.
It is known to divide signal processing circuitry into multiple channels. For example, imagers often include multiple readout channels where one channel processes a specific set of pixel signals and at least one other channel processes the remaining sets of pixel signals. FIG. 7c illustrates a two channel processing circuit 150 designed to sample and hold analog input signals and convert the signals into digital signals. As shown in FIG. 7c, the first channel CHANNEL 1 comprises a sample and hold circuit 152a and multiple analog-to-digital pipeline stages 154a, 156a. Similarly, the second channel CHANNEL 2 comprises a sample and hold circuit 152b and multiple analog-to-digital pipeline stages 154b, 156b. The sample and hold circuits 152a, 152b share an operational amplifier 32. The analog-to-digital pipeline stages 154a, 154b share an operational amplifier 32 as do the other analog-to-digital pipeline stages 156a, 156b.
The devices of the two channels CHANNEL 1, CHANNEL 2 share the operational amplifiers in a similar manner and with similar timing (e.g., FIG. 2) as the adjacent pipelined analog-to-digital converter stages share the operational amplifiers (as discussed above). That is, the channels switch in or out the amplifier based on the operation being performed in that portion of the channel. Thus, although the circuit 150 achieves the benefits of reducing the number of operational amplifiers, the circuit 150 also suffers from the memory effect. Accordingly, there is a need and desire for sharing an operational amplifier between two channels of a signal processing circuit, yet does not suffer from the memory effect and the problems associated with the memory effect.